There are many memory devices that have different voltage threshold (Vt) states by storing different amounts of charges in their memory cells. A two-sided memory device cell has a transistor with two sides (i.e., the drain or source side of a transistor) separated by a channel in the substrate for storing a charge as shown in FIG. 1 of U.S. Pat. No. 5,768,192 (Eitan). However, the voltage threshold (Vt) state of one side of the memory cell could interact with the other side of the memory cell during an operation. This interaction between the sides of the memory cell makes it difficult to analyze or to predict the Vt variation during the memory device operation.
Prior art, such as U.S. Pat. No. 6,320,784 (Muralidhar et al.) at column 2, lines 32–36, discusses a method for programming nanocrystals. However, no threshold state interaction analysis is discussed for this device for each side of the memory cell. In addition, U.S. Pat. No. 5,768,192 (Eitan) at column 2, lines 41–65 and column 3, line 16 through column 4, line 3, discusses the operation of NROM cells. However, two-sided voltage threshold analysis is not presented to show the interaction from one side of the memory cell to the other side of the memory cell. Furthermore, a paper published in the International Electron Devices Meeting Digest, 2002, pages 931–934 (Yeh et al.) discusses the operation of PHINES cells and the threshold voltage for each operating condition, but does not discuss an analysis method of the two-sided voltage threshold interactions for its memory cell.